This application claims priority to Korean Patent Application No. 2002-41950, filed on Jul. 18, 2002, the entire contents of which are incorporated herein by reference.
The present invention is related to the field of integrated circuit devices and methods of operating in general, and more particularly, to integrated circuit memory devices and operations thereof.
As is well known, integrated circuits, such as semiconductor memory devices, can include an array of memory cells as a region for storing information. In order to provide stable read/write operations, an internal power supply voltage (hereinafter, referred to as an internal power supply voltage for the array) is supplied to the array of memory cells in addition to an internal power supply voltage supplied to a peripheral circuit. The internal power supply voltage for the array can be obtained using a circuit for converting an external power supply voltage, which is referred to as an internal voltage generating circuit. The internal voltage generating circuit can be implemented using a differential amplifier and a driver, as is well known to those skilled in the art.
The array of memory cells, in general, can be separated into a plurality of banks that operate independently. The banks can be supplied with the internal power supply voltage for the array via a single power line. A semiconductor memory device can include internal voltage generating circuits corresponding to each of the banks. The internal voltage generating circuits are commonly connected to a single power line so as to output an internal power supply voltage for each of the respective arrays. The internal voltage generating circuits can be controlled so as to operate simultaneously or selectively.
According to FIG. 1, an array of memory cells is formed of four banks and four internal voltage generating circuits are provided to correspond to each of the respective banks. Furthermore, according to FIG. 1, only one of the internal voltage generating circuits operates at one time. In particular, the corresponding internal voltage generating circuit will operate when the corresponding signal (IVC_Active_A, IVC_Active_B, IVC_Active_C, and IVC_Active_D) is activated. As a row of a selected bank is activated, current is consumed by memory cells of the selected bank. With current consumption, an internal power supply voltage Vint for an array becomes can be reduced to less than a target voltage. The lowered internal power supply voltage Vint for the array can be restored (i.e., increased) to the target voltage via an internal voltage generating circuit, which is controlled by the corresponding active signal. For example, as shown in FIG. 1, when IVC_Active_A is activated, Vint is reduced during period xe2x80x9cT1xe2x80x9d in FIG. 1. After the lowered internal power supply voltage Vint for the array is restored to the target voltage (period xe2x80x9cT2xe2x80x9d), the internal voltage generating circuit can continue to operate. Accordingly, current may be unnecessarily consumed during the period T2 in FIG. 1 due to the prolonged operation of the memory cells and the internal voltage generating circuit.
The period T1 in FIG. 1 may be shortened by operating all internal voltage generating circuits simultaneously. That is, as illustrated in FIG. 2, as active signals IVC_Active_A, IVC_Active_B, IVC_Active_C, and IVC_Active_D for activating corresponding internal voltage generating circuits are all activated, an internal power supply voltage for the array, which is lowered by row activation in a selected bank, can be more quickly restored to the target voltage. It will be understood that a period denoted by T3 in FIG. 2 is shorter than that denoted by T1 in FIG. 1. However, since all internal voltage generating circuits may only continue to operate after restoration of the internal power supply voltage for the array to the target voltage, current may be unnecessarily consumed for a period T4 which is even longer the period T2 shown in FIG. 1.
With need for a low-voltage and low-power memory device, recently, a new circuit and technique for reducing current consumption may be useful in semiconductor memory devices.
Embodiments according to the present invention can provide internal voltages to memory arrays. Pursuant to these embodiments, an integrated circuit memory device includes a plurality of banks of a memory array and a power line connected to the plurality of banks. A plurality of internal voltage generating circuits are connected in parallel to the power line and are configured to provide internal voltage to the plurality of banks. A control circuit is connected to the plurality of internal voltage generating circuits and is configured to provided the internal voltage to more than one of the plurality of banks during a requested operation performed by fewer than all of the plurality of banks.
In some embodiments according to the present invention, the control circuit can include a bank selector circuit that is configured to select ones of the plurality of banks to receive the internal voltage and a pulse generator circuit, connected to the bank selector circuit, that is configured to generate an enable pulse for an activation time period responsive to the selection of the at least one of the plurality of banks. A plurality of internal voltage generating enable circuits is connected to the pulse generator circuit and the bank selector circuit and is configured to enable all of the plurality of internal voltage generating circuits for the activation time period.
In some embodiments according to the present invention, the plurality of internal voltage generating enable circuits are configured to disable ones of the plurality of internal voltage generating circuits not needed to complete the requested operation after the activation time period elapses.
In some embodiments according to the present invention, the pulse generator circuit includes an OR gate having a plurality of inputs connected to the bank selector circuit and that is configured to provide an output therefrom, a delay circuit connected to the OR gate and that is configured to delay the output of the OR gate for the activation timer period to an output of the delay circuit, an inverter circuit that is connected to the delay circuit and is configured to invert the output of the delay circuit at an output of the inverter circuit, and an AND gate, that is connected to the output of the OR gate and to the output of the inverter circuit, and is configured to provide the enable pulse responsive to the selection by the bank selector circuit.
In some embodiments according to the present invention, the requested operation is a read or write operation to a location in one of the plurality of banks. In some embodiments according to the present invention, the activation time period is a time that is sufficient to restore the internal voltage to a tar get voltage.
In some embodiments according to the present invention, the control circuit provides the internal voltage to more than one of the plurality of banks based address information and control information. In some embodiments according to the present invention, the control circuit further provides the internal voltage to the selected one of the plurality of banks for a requested operation time period and provides the internal voltage to remaining plurality of banks for an activation time period that is less than the requested operation time period.
In some embodiments according to the present invention, the requested operation time period is a time that is sufficient to complete the requested operation to the selected one of the plurality of banks. In some embodiments according to the present invention, the control circuit further provides the internal voltage to all of the plurality of banks if the requested operation is performed by all of the plurality of banks.
In accordance with one aspect of the present invention, there is provided a semiconductor memory device which includes a plurality of banks each of which includes a plurality of memory cells each storing data. A power line transfers an internal power supply voltage to be supplied in common to the banks. A plurality of internal voltage generating circuits are connected in common to the power line and supply the internal power supply voltage to the power line, respectively. A control circuit controls activation of the internal voltage generating circuits in response to bank and command information. When one of the banks is selected, the control circuit makes internal voltage generating circuits corresponding to unselected banks be inactivated after the internal voltage generating circuits are simultaneously activated and a predetermined time elapses. When the banks are all selected, the control circuit makes the internal voltage generating circuits be activated until a bank operation is completed.
In a case where the memory cells are DRAM cells, the predetermined time is an active restore time of the DRAM cells. Alternatively, the predetermined time is 80% of an active restore time of the DRAM cells.